This invention relates to the field of solid state electronics, and particularly to a lithographic method to provide good lift-off when removing unwanted material during the processing of integrated circuits.
Current state of the art integrated circuit manufacturing requires processing methods capable of consistently producing microscopic pattern geometries. The dimensions of circuit features are routinely measured in microns (10.sup.-6 meter). Processing methods are now required to produce fine pattern definition of metal or dielectric films in submicron dimensions.
The lift-off process is used in the fabrication of integrated circuits to define metal or dielectric film patterns on the substrate (wafer) surface. These patterns are used, for example, to connect circuit devices together with metal wiring. To complete a multilevel circuit, as many as four or five liftoff steps may be necessary. The liftoff process is particularly useful to fabricate integrated circuits on substrates such as gallium arsenide which utilize metallization and dielectric layers which are not easily removed by etching. The problems involved with the lift-off process influence and place practical constraints upon the design and manufacture of successful circuits on gallium arsenide, particularly as the circuit density moves into large scale and very large scale levels of integration (LSI and VLSI).
In general, the lift-off process utilizes three steps, as follows:
Step 1. A light sensitive photoresist emulsion is uniformly applied to the substrate surface. The photoresist is exposed by optical light or electron beam through a mask which defines a pattern on the substrate. The pattern is developed and the resist is baked to stabilize.
Step 2. Next the required metal or dielectric film is deposited on the patterned substrate. The deposition of material is done in a vacuum system by physical vapor evaporation or sputtering.
Step 3. Then liftoff of the unwanted film material around the pattern occurs by dissolving the photoresist in a suitable solvent such as acetone. The solvent can be sprayed on the substrate, or a solvent bath agitated by ultrasonic can be used to aid the liftoff process. The end result is the unwanted material rinses away leaving the patterned area intact on the wafer surface.
The problem with the liftoff process is in removing the unwanted film around the pattern cleanly and leaving a clearly defined pattern planar to the substrate surface with no irregularities. The last statement is the definition of a "good liftoff".
There are three problems which can affect the achievement of a good liftoff:
1. Retention--The worst case problem for the liftoff process is when the unwanted film material will not separate from the pattern. Large areas of the substrate are left covered with material that will not lift off. Consequently, the pattern definition is extremely poor as shown in FIG. 1.
2. Ears--Deposited film material standing perpendicular to the substrate along the edge profile (sidewalls) of the pattern (FIG. 2). The ears can become a source of shorts in the circuit by protruding through subsequent layers. These ears get larger with increasing thickness of the deposited film.
3. Redeposition--Particles of material being rinsed away during the liftoff which become reattached to the substrate in random locations. Redeposition can occur in varying degrees of severity and its effect is to reduce the device yield.
Attempts have been made in the prior art to overcome these problems. For example, K. R. Grete (U.S. Pat. No. 3,849,136) describes the use of an aluminum layer and undercutting of the aluminum layer at the sidewall by overexposure to avoid edge tearing. Janos, et al. (U.S. Pat. No. 4,202,914) describe reactive ion etching an organic polymeric material under a silicon nitride layer to provide a discontinuity between a film on the substrate and the same film on the pattern layer. Homma, et al (IEEE Transactions on Electron Devices, Vol. Ed-28, No. 5, May 1981) describe the use of a molybdenum mask formed on polyimide to provide an undercut pattern for use when applying a metal layer to a substrate. The Gete, Janos et al, and Homma et al processes are bi-level photoresist type processes. A single-level photoresist process is described by M. Hatzakis, et al (IBM J. Res. Develop., Vol. 24, No. 4, July 1980) in which chlorobenzene is used to modify the top of the photoresist layer and thus provide and undercut the resist profile. H. Klose, et al (IEEE Transactions on Electron Devices, Vol. ed-32, No. 9, September, 1985) describe results obtained using a single-level negative photoresist process patented by Moritz and Paal (U.S. Pat. No. 4,104,070). In these prior art processes, the integrated circuit material is deposited directly upon the substrate in a single deposition step. However, the use of these prior art processes for submicron geometries has not been completely successful, and more reliable and economical processes are continually needed.